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Freescale Semiconductor Technical Data
Document Number: MC33395
Rev 4.0, 2/2007
Three-Phase Gate Driver IC
The 33395 simplifies the design of high-power BLDC motor control design by combining the gate drive, charge pump, current sense, and protection circuitry necessary to drive a three-phase bridge configuration of six N-channel power MOSFETs. Mode logic is incorporated to route a pulse width modulation (PWM) or a complementary PWM output signal to either low-side or high-side MOSFETs of the bridge. Detection and drive circuitry are also incorporated to control a reverse battery protection high-side MOSFET switch. PWM frequencies up to 28 kHz are possible. Built-in protection circuitry prevents damage to the MOSFET bridge as well as the drive IC and includes overvoltage shutdown, overtemperature shutdown, overcurrent shutdown, and undervoltage shutdown. The device is parametrically specified over ambient temperature range of -40C TA 125C and 5.5 V VIGN 24 V supply. Features * Drives Six N-Channel Low RDS(ON) Power MOSFETs * Built-In Charge Pump Circuitry * Built-In Current Sense Comparator and Output Drive Current Limiting * Built-In PWM Mode Control Logic * Built-In Circuit Protection * Designed for Fractional to Integral HP BLDC Motors * 32-Pin SOIC Wide Body Surface Mount Package * 33395 Incorporates a <5.0 s Shoot-Through Suppression Timer * 33395T Incorporates a <1.0 s Shoot-Through Suppression Timer * Pb-Free Packaging Designated by Suffix Code EW
33395 33395T
THREE-PHASE GATE DRIVER IC
DWB SUFFIX EW SUFFIX (Pb-FREE) 98ARH99137A 32-PIN SOICW
ORDERING INFORMATION
Device MC33395DWB/R2 MC33395EW/R2 MCZ33395EW/R2 MC33395TDWB/R2 MC33395TEW/R2 - 40C to 125C 32 SOICW 32 SOICW (Pb-Free) Temperature Range (TA) Package 32 SOICW 32 SOICW (Pb-Free)
VPWR
33395
VDD VGDH VIGN VDD CP1H CP1L CP2H CP2L CRES 3 2 3 VIGNP GDH1 GDH2 GDH3 SRC1 SRC2 SRC3 N S N
H
S
H
H
MCU
HSE1-3 MODE0-1 GDL1 GDL2 PWM GDL3 LSE1-3 -ISENS AGND PGND +ISENS
VDD
Figure 1. 33395 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice. (c) Freescale Semiconductor, Inc., 2007. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VIGN VDD Osc. Low Low Voltage Reset Reset Charge Charge Pump Overvoltage Overvoltage Shutdown CP1H CP1L CP2H CP2L CPRES +ISENS -ISENS + -
Drive Limiting Drive Limiting L H VGDH Control Control Logic Logic VIGNP Gate Drive Gate Circuits Drive Circuits GDH1 GDH2 GDH3 SRC1 SRC2 SRC3 GDL1 GDL2 GDL3
MODE0 MODE1 PWM HSE1 HSE2 HSE3 LSE1 LSE2 LSE3 AGND TEST PGND Overtemperature Shutdown Shutdown
Figure 2. 33395 Simplified Internal Block Diagram
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
CP2H CPRES VIGN VGDH VIGNP SRC1 GDH1 GDL1 SRC2 GDH2 GDL2 SRC3 GDH3 GDL3 PGND TEST
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
CP2L CP1H CP1L LSE1 LSE2 LSE3 HSE1 HSE2 HSE3 MODE0 MODE1 PWM VDD AGND +ISENS -ISENS
Figure 3. 33395 Pin Connections Table 1. 33395 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 9.
Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pin Name CP2H CPRES VIGN VGDH VIGNP SRC1 GDH1 GDL1 SRC2 GDH2 GDL2 SRC3 GDH3 GDL3 PGND Test -ISENS +ISENS AGND VDD PWM Input Input Output Input Sensor Output Output Sensor Output Output Sensor Output Output Ground N/A Input Input Ground Power Input Pin Function Formal Name Charge Pump Cap Charge Pump Reserve Cap Input Voltage High-Side Gate Voltage Input Voltage Protected High-Side Sense Gate Drive High Output for Gate High-Side Sense Gate Drive High Output for Gate High-Side Sense Gate Drive High Gate Drive Low Power Ground Test Pin IS Minus IS Plus Analog Ground Logic Supply Voltage Definition High potential pin connection for secondary charge pump capacitor Input from external reservoir capacitor for charge pump Input from ignition level supply voltage for power functions Output full-time gate drive for auxiliary high-side power MOSFET switch Input from protected ignition level supply for power functions Sense for high-side source voltage, phase 1 Output for gate high-side, phase 1 Output for gate drive low-side, phase 1 Sense for high-side source voltage, phase 2 Output for gate high-side, phase 2 Output for gate drive low-side, phase 2 Sense for high-side source voltage, phase 3 Output for gate drive high-side, phase 3 Output for gate drive low-side, phase 3 Ground pins for power functions This should be connected to ground or left open Inverting input for current limit comparator Non-inverting input for current limit comparator Ground pin for logic functions Supply voltage for logic functions
Pulse Width Modulator Input for pulse width modulated driver duty cycle
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Analog Integrated Circuit Device Data Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 33395 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 9.
Pin Number 22 23 24 25 26 27 28 29 30 31 32 Pin Name MODE1 MODE0 HSE3 HSE2 HSE1 LSE3 LSE2 LSE1 CP1L CP1H CP2L Pin Function Input Input Input Input Input Input Input Input Input Input Input Formal Name Mode Control Bit 1 Mode Control Bit 0 High-Side Enable High-Side Enable High-Side Enable Low-Side Enable Low-Side Enable Low-Side Enable External Pump Capacitor External Pump Capacitor Charge Pump Capacitor Definition Input for mode control selection Input for mode control selection Input for high-side enable logic, phase 3 Input for high-side enable logic, phase 2 Input for high-side enable logic, phase 1 Input for low-side enable logic, phase 3 Input for low-side enable logic, phase 2 Input for low-side enable logic, phase 1 Input from external pump capacitor for charge pump and secondary pins Input from external pump capacitor for charge pump and secondary pins Input from external reservoir, external pump capacitors for charge pump, and secondary pins
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings All voltages are with respect to ground unless otherwise noted.
Rating VIGN Supply Voltage VIGNP Load Dump Survival VDD Logic Supply Voltage (Fail Safe) Logic Input Voltage (LSEn, HSEn, PWM, and MODEn) Start Up Current VIGNP ESD Voltage
(1)
Symbol VIGN VIGNP
LD
Value -15.5 to 40 -0.3 to 65 -0.3 to 7.0 0.3 to 7.0 100
Unit VDC VDC VDC VDC mA V
VDD VIN IVIGNSTARTUP
Human Body Model Machine Model Storage Temperature Operating Ambient Temperature Operating Case Temperature Maximum Junction Temperature Power Dissipation (TA = 25C) Peak Package Reflow Temperature During Reflow Thermal Resistance, Junction-to-Ambient
(2), (3)
VESD1 VESD2 TSTG TA TC TJ PD TPPRT RJA
500 200 -65 to 160 -40 to 125 -40 to 125 150 1.5 Note 3 65 C C C C W C C/ W
Notes 1. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ). 2. 3. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics Characteristics noted under conditions -40C TA 125C, 5.5 V VIGNP 24 V unless otherwise noted. Typical values reflect approximate parameter mean at TA = 25C under normal conditions unless otherwise noted.
Characteristic POWER INPUT VIGN Current @ 5.5 V - 24 V, VDD = 5.5 V VIGNP Current @ 5.5 V - 24 V, VDD = 5.5 V VIGNP Overvoltage Shutdown VIGNP Voltage VDD Current @ 5.5 VDC, 5.5 V VIGNP 24 V VDD Low-Voltage Reset Level VDD One-Time Fuse (Logic Supply) INPUT / OUTPUT Input Current at VDD = 5.5 V LSEn, HSEn, PWM, and MODEn = 3.0 V Input Threshold at VDD = 5.5 V LSEn, HSEn, PWM, and MODEn (4) VSCRn Source Sense Voltage SRC1, SRC2, SRC3 Comparator Input Offset Voltage Comparator Input Bias Current Comparator Input Offset Current Common Mode Voltage
(5) (5)
Symbol
Min
Typ
Max
Unit
IIGN IIGNP VIGNP
SD
- - 25 5.5 - 2.5 7.0
0.2 - 33 - 1.8 3.2 -
1.0 100 36.5 24 4.0 4.0 -
mA mA V V mA V V
VIGNP I
VDD
VDD(RESET) -
IIN 5.0 VTH 1.0 VSCRn -0.3 VINP(OFFSET) VINP(BIAS) IINP(OFFSET) VCMR VINPdiff VCRES - VIGNP 4.0 4.0 4.5 8.0 4.5 VGDHn(on) - V SRCn 4.0 4.0 4.5 VGDHn(off) -1.0 0.6 1.0 5.2 9.0 11 18 18 18 6.0 7.5 10 16 12 18 18 18 18 18 5.0 -500 -300 0 -VDD VIGNP 14 -170 -3.0 - - 24 20 500 300 VDD - 2.0 +VDD 2.0 3.0 12 25
A
V
V
mV nA nA VDC V V
Comparator Differential Input Voltage Charge Pump Voltage VIGN
(6)
VIGNP = 5.5 V, ICRES = 1.0 mA VIGNP = 9.0 V, ICRES = 1.0 mA VIGNP = 12 V, ICRES = 5.0 mA VIGNP = 24 V, ICRES = 1.0 mA VIGNP = 24 V, ICRES = 5.0 mA VGDH Output Voltage with GDHn in ON State VIGNP = 5.5 V, IGDHn = 1.0 mA VIGNP = 12 V, IGDHn = 5.0 mA VIGNP = 24 V, IGDHn = 5.0 mA VGDH Output Voltage with GDHn in OFF State VIGNP = SRCn = 14 V, IGDHn = 1.0 mA
V
V
Notes 4. Logic inputs LSEn, HSEn, PWM, and MODEn have internal 20 A internal sinks. 5. Guaranteed by design and characterization. Not production tested. 6. The Charge Pump has a positive temperature coefficient. Therefore the Min's occur at -40C, Typ's at 25C, and Max's at 125C.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued) Characteristics noted under conditions -40C TA 125C, 5.5 V VIGNP 24 V unless otherwise noted. Typical values reflect approximate parameter mean at TA = 25C under normal conditions unless otherwise noted.
Characteristic INPUT / OUTPUT (CONTINUED) VGDL Low-Side Output Voltage GDHn in ON State VIGNP = 5.5 V, IGDLn = 1.0 mA VIGNP = 12 V, IGDLn = 5.0 mA VIGNP = 24 V, IGDLn = 0.0 mA VIGNP = 24 V, IGDLn = 5.0 mA VGDL Output Voltage GDHn in OFF State VIGNP = 14 V, IGDLn = 1.0 mA Thermal Shutdown (7) TLIM VGDL(off) -1.0 160 0.3 - 1.0 190 C VGDL(on) 5.0 8.0 8.0 8.0 8.0 14 17 16 18 18 19 19 V V Symbol Min Typ Max Unit
Notes 7. Guaranteed by design and characterization. Not production tested.
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics Characteristics noted under conditions -40C TA 125C, 5.5 V VIGNP 24 V unless otherwise noted. Typical values reflect approximate parameter mean at TA = 25C under normal conditions unless otherwise noted.
Characteristic High-Side (GDHn) and Low-Side Drivers (GDHn) Rise Time (25% to 75%), CISS Value = 2000 pF
(8)
Symbol t RH
Min
Typ
Max
Unit s
- t FH - t D1, t D2 1.0 0.2
0.35
1.5 s
High-Side (GDHn) and Low-Side Drivers (GDHn) Fall Time (75% to 25%), CISS Value = 2000 pF (8) Shoot-Through Suppression Time Delay (33395) (8), (9) 33395 33395T Current Limit Time Delay
(10)
0.25
1.5 s
3.0 0.65 2.8
5.5 1.0 5.0 s
t ILIMDELAY
1.5
Notes 8. See Figure 4, page 8. 9. Shoot-Through Suppression Time Delay is provided to prevent directly connected high- and low-side MOSFETs from being on simultaneously. 10. Current Limit Time Delay: The internal comparator places the device in the current limit mode when the comparator output goes LOW and sets an internal logic bit. This takes a finite amount of time and is stated as the Current Limit Time Delay.
TIMING DIAGRAM
GDHn SRCn (%)
100 75
25 0 tD1
tRH tFH
tD2
tRL
GDLn, Gate V (%)
100 75 25 0
tFL
TIME
Figure 4. Shoot-Through Suppression
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 33395 and 33395T devices are designed to provide the necessary drive and control signal buffering and amplification to enable a DSP or MCU to control a threephase array of power MOSFETs such as would be required to energize the windings of powerful brushless DC (BLDC) motors. It contains built-in charge pump circuitry so that the MOSFET array may consist entirely of N-Channel MOSFETs. It also contains feedback sensing circuitry and control circuitry to provide a robust overall motor control design.
FUNCTIONAL PIN DESCRIPTION CHARGE PUMP CAPACITOR (CP2H)
High potential pin connection for secondary charge pump capacitor
IS MINUS (-ISENS)
Inverting input for current limit comparator
IS PLUS (+ISENS) CHARGE PUMP RESERVE CAPACITOR (CPRES)
Input from external reservoir capacitor for charge pump Non-Inverting input for current limit comparator
ANALOG GROUND (AGND) INPUT VOLTAGE (VIGN)
Input from ignition level supply voltage for power functions Ground pin for logic functions
LOGIC SUPPLY VOLTAGE (VDD) HIGH-SIDE GATE VOLTAGE (VGDH)
Output full-time gate drive for auxiliary high-side power MOSFET switch Supply voltage for logic functions
PULSE WIDTH MODULATOR (PWM)
Input for pulse width modulated driver duty cycle
INPUT VOLTAGE PROTECTED (VIGNP)
Input from protected ignition level supply for power functions
MODE CONTROL BIT 1 (MODE1)
Input for mode control selection
HIGH-SIDE SENSE (SRC1, SRC2, SRC3)
Sense for high-side source voltage, phase 1/2/3
MODE CONTROL BIT 0 (MODE0)
Input for mode control selection
GATE DRIVE HIGH (GDH1, GDH2, GDH3)
Output for gate high-side, phase 1/2/3
HIGH-SIDE ENABLE (HSE3, HSE2, HSE1)
Input for high-side enable logic, phase 1/2/3
OUTPUT FOR GATE (GDL1, GDL2, GDL3)
Output for gate drive low-side, phase 1
LOW-SIDE ENABLE (LSE3, LSE2, LSE1)
Input for low-side enable logic, phase 1/2/3
POWER GROUND (PGND)
Ground pins for power functions
EXTERNAL PUMP CAPACITOR (CP1L, CP1H)
Input from external pump capacitor for charge pump and secondary pins
TEST PIN (TEST)
This should be connected to ground or left open
CHARGE PUMP CAPACITOR (CP2L)
Input from external reservoir, external pump capacitors for charge pump, and secondary pins
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Analog Integrated Circuit Device Data Freescale Semiconductor
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FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
FUNCTIONAL INTERNAL BLOCK DESCRIPTION GATE DRIVE CIRCUITS
The gate drive outputs (GDH1, GDH2, etc.) supply the peak currents required to turn ON and hold ON the MOSFETs, as well as turn OFF and hold OFF the MOSFETs.
LOW VOLTAGE RESET FUNCTION
When the logic supply voltage (VDD) drops below the minimum voltage level or when the part is initially powered up, this function will turn OFF and hold OFF the external MOSFETs until the voltage increases above the minimum voltage level required for normal operation.
CHARGE PUMP
The current capability of the charge pump is sufficient to supply the gate drive circuit's demands when PWMing at up to 28 kHz. Two external charge pump capacitors and a reservoir capacitor are required to complete the charge pump's circuitry. Charge reservoir capacitance is a function of the total MOSFET gate charge (QG) gate drive voltage level relative to the source (VGS) and the allowable sag of the drive level during the turn-on interval (VSAG). CRES can be expressed by the following formula: CRES = QG x VGS 2 x VGS x VSAG - VSAG2
CONTROL LOGIC
The control logic block controls when the low-side and high-side drivers are enabled. The logic implements the Truth Table found in the specification and monitors the M0, M1, PWM, CL, OT, OV, LSE, and HSE pins. Note that the drivers are enabled 3 s after the PWM edge. During complimentary chop mode the high-side and low-side drives are alternatively enabled and disabled during the PWM cycle. To prevent shoot-through current, the high-side drive turn-on is delayed by tD1, and the low-side drive turn on is delayed by tD2 (see Figure 4, page 8). Note that the drivers are disabled during an overtemperature or overvoltage fault. A flip-flop keeps the drive off until the following PWM cycle. This prevents erratic operation during fault conditions. The current limit circuit also uses a flip-flop for latching the drive off until the following PWM cycle. Note PWM must be toggled after POR, Thermal Limit, or overvoltage faults to re-enable the gate drivers.
For example, for QG = 60 nC, VGS = 14 V, VSAG = 0.2 V: CRES = (60 nC) x (14 V) = 0.15 F 2 x (14 V) x (0.2 V) - (0.2)2
Proper charge pump capacitance is required to maintain, and provide for, adequate gate drive during high demand turn-ON intervals. Use the following formula to determine values for CP1 and CP2: For example, for the above determination of CRES = 0.15 F: CRES 20 < CP1 = CP2 < CRES 10
VGDH
The VGDH pin is used to provide a gate drive signal to a reverse battery protection MOSFET. If reverse battery protection is desired, VIGN would be applied to the source of an external MOSFET, and the drain of the MOSFET would then deliver a "protected" supply voltage (VIGNP) to the three phase array of external MOSFETs as well as the supply voltage to the VIGNP pin of the IC. In a reverse polarity event (e.g., an erroneous installation of the system battery), the VGDH signal will not be supplied to the external protection MOSFET, and the MOSFET will remain off and thus prevent reverse polarity from being applied to the load and the VIGNP supply pin of the IC.
By averaging these two values, the proper CPn value can be determined:
0.15 F 20 = 0.075 F, lower limit; and 0.15 F 10 = .015 F, upper lim
CP1 and CP2 =(0.0075 F + 0.015 F) / 2 = 0.01 F
HIGH-SIDE GATE DRIVE CIRCUITS THERMAL SHUTDOWN FUNCTION
The device has internal temperature sensing circuitry which activates a protective shutdown function should the die reach excessively elevated temperatures. This function effectively limits power dissipation and thus protects the device. Outputs GDH1, GDH2, and GDH3 provide the elevated drive voltage to the high-side external MOSFETs (HS1, HS2, and HS3; see Figure 5, page 13). These gate drive outputs supply the peak currents required to turn ON and hold ON the high-side MOSFETs, as well as turn OFF the MOSFETs. These gate drive circuits are powered from an internal charge pump, and therefore compensate for voltage dropped across the load that is reflected to the source-gate circuits of the high-side MOSFETs.
OVERVOLTAGE SHUTDOWN FUNCTION
When the supply voltage (VIGN) exceeds the specified over- voltage shutdown level, the part will automatically shut down to protect both internal circuits as well as the load. Operation will resume upon return of VIGN to normal operating levels.
33395
LOW-SIDE GATE DRIVE CIRCUITS
Outputs GDL1, GDL2, and GDL3 provide the drive voltage to the low-side external MOSFETs (LS1, LS2, and LS3; see
10
Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION
Figure 5). These gate drive outputs supply the peak currents required to turn ON and hold ON the low-side MOSFETs, as well as turn OFF the MOSFETs.
to occur on both the high-side and low-side MOSFETs as "complementary chopping".
TEST PIN VDD FUSE
The VDD supply of the 33395 IC has an internal fuse, which will blow and set all outputs of the device to OFF, if the VDD voltage exceeds that stated in the maximum rating section of the data sheet. When this fuse blows, the device is permanently disabled. This pin should be grounded or left floating (i.e., do not connect it to the printed circuit board). It is used by the automated test equipment to verify proper operation of the internal overtemperature shut down circuitry. This pin is susceptible to latch-up and therefore may cause erroneous operation or device failure if connected to external circuitry.
ISENS INPUTS
The +Isens and -Isens pins are inputs to the internal current sense comparator. In a typical application, these would receive a a low-pass filtered voltage derived from a current sense resistor placed in series with the ground return of the three-phase output bridge. When triggered by the comparator, the CL (current limit) bit of the internal error register is set, and the output gate drive pairs (i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and GDL3), are controlled such that current will cease flowing through the load (refer to Table 5, Truth Table, page 12).
OVERTEMPERATURE AND OVERVOLTAGE SHUTDOWN CIRCUITS
Internal monitoring is provided for both over temperature conditions and over voltage conditions. When any of these conditions presents itself to the IC, the corresponding internally set bits of the error register are set, and the output gate drive pairs (i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and GDL3), are controlled such that current will cease flowing through the load (refer to Table 5).
LSE AND HSE INPUT CIRCUITS
The low-side enable input pins (LSE1, LSE2, LSE3) and high-side enable input pins (HSE1, HSE2, HSE3) form the input pairs (HSE1 and LSE1, HSE2 and LSE2, HSE3 and LSE3) which set the logic states of the output gate drive pairs (i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and GDL3) in accordance with the logic set forth in the Truth Table (page 12). Typically these inputs are supplied from an MCU or DSP to provide the phasing of the currents applied to a brushless dc motor's stator coils via the output MOSFET pairs.
PWM INPUT
The pulse width modulation input provides a single input pin to accomplish PWM modulation of the output pairs in accordance with the states of the Mode 0 and Mode 1 inputs as set forth in the Truth Table (page 12).
MODE SELECTION INPUTS
The mode selection inputs (Mode 0 and Mode 1) determine the PWM implementation of the output pairs in accordance with the logic set forth in the Truth Table (page 12). PWMing can thus be set to occur either on the high-side MOSFETs or the low-side MOSFETs, or can be set
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Table 5. Truth Table The logic state of each output pair, GDLn and GDHn (n = 1, 2, 3), is a function of its corresponding input pair, LSEn and HSEn (n = 1, 2, 3), along with the logic states of the MODEn and PWM inputs and the internally set overtemperature shutdown (OT), overvoltage (OV), and current limit (CL) bits provided in this table.
NORMAL OPERATION Switching Modes MODE1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MODE0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Internally Set Bits OT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Input Pairs (e.g., LSE2 and HSE2) LSEn 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 HSEn 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Pairs (e.g., GDL2 and GDH2) GDLn 0 0 PWM 0 0 0 PWM 0 0 0 1 0 0 PWM 1 0 GDHn 0 1 0 0 0 1 PWM 0 0 PWM 0 0 0 PWM 0 0
FAULT MODE OPERATION Switching Modes MODE1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x x MODE0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x x Internally Set Bits OT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 1 OV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 x CL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 x x Input Pairs (e.g., LSE2 and HSE2) LSEn 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 x x HSEn 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 x x Output Pairs (e.g., GDL2 and GDH2) GDLn 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 GDHn 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0
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Analog Integrated Circuit Device Data Freescale Semiconductor
TYPICAL APPLICATIONS OPERATIONAL MODES
TYPICAL APPLICATIONS
+
12 V
HS1
HS2
HS3
+ -
SRC1 GDH1 GDL1 SRC2 GDH2 GDL2 SRC3 GDH3 GDL3 PGND TEST
LSE1 LSE2 LSE3 HSE1 HSE2 HSE3 MODE0 MODE1 PWM VDD AGND +ISENS -ISENS
MCU
LS1 5.0 V + LS2 LS3
Figure 5. Typical Application Diagram
RSENSE
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Analog Integrated Circuit Device Data Freescale Semiconductor
TO MOTOR
CP2H CPRES VIGN VGDH VIGNP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
CP2L CP1H CP1L
13
PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the 98ARH99137A listed below.
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4 MM PER SIDE. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
10.3 7.6 7.4 C 5
1 32
B 9
2.65 2.35
30X
0.65
PIN 1 ID 4 B 9 11.1 10.9 C L
16
17
5.15
2X 16 TIPS
A
32X
SEATING PLANE
0.3 A B C A (0.29) 0.25 0.19 A 6 0.13
M BASE METAL
0.10 A
(0.203) 0.38 0.22 CA
M
R0.08 MIN 0.25
GAUGE PLANE
0
MIN
PLATING
0.29 0.13
B
8 8 0 0.9 0.5 SECTION B-B
ROTATED 90 CLOCKWISE
SECTION A-A
DWB SUFFIX EW SUFFIX (PB-FREE) 32-PIN PLASTIC PACKAGE 98ARH99137A ISSUE A
33395
14
Analog Integrated Circuit Device Data Freescale Semiconductor
REVISION HISTORY
REVISION HISTORY
REVISION 3.0
DATE 7/2005
DESCRIPTION OF CHANGES * * * * * * Implemented Revision History page Converted to Freescale format Added Pin Definitions Updated Freescale data sheet form and style Added MCZ33395EW/R2 to the Ordering Information block Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter and added notes (2) and (3) to Maximum Ratings on page 5
4.0
2/2007
33395
Analog Integrated Circuit Device Data Freescale Semiconductor
15
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MC33395 Rev 4.0 2/2007

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